1. Field of the Invention
The present invention relates to the transmission of digital data, and, in particular, to the recovery of clock timing at the receiving side.
Certain terms used in this specification are defined as follows. First, "sampling clock signal" means a clock signal used for sampling in a demodulator. Next, "clock timing" means the timing of the sampling clock signal when the bit error rate is a minimum. Finally, "symbol rate" means the rate at which the main signal changes, i.e., the modulation rate.
2. Description of the Related Art
The growth of multimedia communications in recent years has necessitated the provision of multimedia wireless communication systems capable of high-speed transmission of digital data in burst form. Examples of such systems include high-speed wireless local area networks (LANs) and future public land mobile telecommunication. To process digital data at high speeds without bit errors, it is essential to have, at the receiving side of these wireless communication systems, a clock timing recovery circuit which rapidly establishes the clock timing using a signal for clock timing recovery added to the front of a burst of digital data, and which subsequently tracks fluctuations in clock timing. A clock timing recovery circuit which tracks fluctuations in clock timing is also necessary when transmitting continuous digital data.
Conventional clock timing recovery circuits can be broadly divided into circuits which recover clock timing at the symbol rate by analog processing, and circuits which recover clock timing by digital processing after oversampling. A tank-limiter clock recovery circuit using IF signal operation is an example of the former, while a clock recovery circuit using a binary quantized digital phase-locked loop (BQDPL) is an example of the latter. Examples of the configuration of these two conventional kinds of clock timing recovery circuit are explained below.
FIG.1 shows an example of the configuration of a demodulator provided with a tank-limiter clock recovery circuit using IF signal operation. This demodulator comprises a quadrature detector 1 to which the IF signal is input, analog-to-digital converters 2 and 3, which sample the outputs of quadrature detector 1, a baseband signal processing circuit 4, which obtains decoded signals by processing the sampled signals that are output by analog-to-digital converters 2 and 3, and a tank-limiter clock recovery circuit using IF signal operation 200 for recovering the clock timing. Tank-limiter clock recovery circuit using IF signal operation 200 comprises an envelope detection circuit 201, a tank circuit 202 and a limiter circuit 203.
The IF signal is input to envelope detection circuit 201, which extracts the clock frequency component by nonlinear processing of the IF signal, which does not itself contain the clock frequency component. Tank circuit 202 comprises a narrowband band-pass filter and reduces clock jitter. Limiter circuit 203 shapes the sinusoidal clock signal obtained by tank circuit 202 into a square wave. If sampling is performed using the clock signal obtained in this way, the bit error rate is minimized. This clock signal 300 is supplied to various sections of the demodulator, including analog-to-digital converters 2 and 3.
A detailed explanation of a tank-limiter clock recovery circuit using IF signal operation is given in "TDMA Communications" by Yamamoto and Kato, published by the IEICE Japan.
FIG. 2 shows an example of the configuration of a demodulator provided with a clock recovery circuit using a binary quantised digital phase-locked loop (BQDPL). A flowchart of the operation of this BQDPL clock recovery circuit is given in FIG.3. The demodulator comprises a quadrature detector 1 to which the IF signal is input, analog-to-digital converters 2 and 3, which sample the output of quadrature detector 1, a baseband signal processing circuit 4, which obtains demodulated signals by processing the sampled signals that are output by analog-to-digital converters 2 and 3, and a BQDPL clock recovery circuit 210 which recovers the clock timing. BQDPL clock recovery circuit 210 comprises a zero-crossing detector 211, phase decision circuit 212, loop filter 213, and VCO (voltage-controlled oscillator) 214.
Analog-to-digital converters 2 and 3 and baseband signal processing circuit 4 operate at twice the symbol rate, and input to BQDPL clock recovery circuit 210 the sampled signal obtained by sampling at twice the symbol rate. Sampled signal D(t+nT)208, which has the same period as the symbols, is input to zero-crossing detector 211. (T is the symbol period and n is an arbitrary integer.) When the sign of the input signal inverts (i.e., when a zero-crossing occurs) zero-crossing detector 211 sends notification of this to phase decision circuit 212. Sampled signal D(t+nT) 302 is then input to phase decision circuit 212 along with sampled signal D{t+(n-1/2)T} which has been sampled with a timing leading D(t+nT) by T/2. Phase decision circuit 212 decides, on the basis of the signs of the two signals, whether the sampling timing leads or lags the clock timing (at which the bit error rate is minimum). In other words, if D(t+nT).times.D{t+(n-1/2)T} is positive, it decides that the sampling timing lags, and if it is negative, it decides that it leads. Phase decision circuit 212 outputs a decision result only when zero crossing detector 211 has detected a zero crossing. Loop filter 213 is an integrating circuit and integrates the decision results of phase decision circuit 211, and on the basis of the result of this integration controls the frequency of the clock (twice the symbol rate) output by VCO 214. The result of this processing is that any lead or lag of the sampling timing is regulated and a clock timing having a minimum bit error rate is obtained. This clock signal 304 is supplied to various sections of the demodulator, including analog-to-digital converters 2 and 3.
A detailed explanation of a BQDPL clock recovery circuit is given in "Digital Communications By Satellite" by V. K. Bhargava, D. Haccoun, R. Matyas and P. P. Nuspl, New York: Wiley, 1981.
Tank-limiter clock recovery circuits using IF signal operation and BQDPL clock recovery circuits are both widely employed in receivers used when low-speed digital data is being transmitted. However, several problems are encountered in receiving high-speed digital data. These problems are explained below.
A tank-limiter clock recovery circuit using IF signal operation employs a tank circuit, which is a narrowband band-pass filter, to reduce clock jitter. To reduce clock jitter, the Q of the tank circuit has to be made large (Q=f.sub.0 /.DELTA.f, where f.sub.0 is the center frequency of the filter and .DELTA.f is the 3-dB bandwidth). However, the delay of a single-tuned resonator, which is generally used as a tank circuit, can be expressed as approximately Q/4 (symbols). Accordingly, if the Q is made large, the delay of the tank circuit is lengthened, so that more time is needed to recover the clock timing. For example, in a wireless LAN system conforming to RCR standard STD-34A, "19GHz Band Data Transmission Radio Equipment for Premises Radio Station", established by the Research & Development Centre for Radio Systems, the Q required to obtain a good bit error rate is around 110. In this case, the delay is approximately 28 symbols, which means that considerable time is needed to recover the clock timing. Moreover, because this circuit is an analog circuit, it is difficult to reduce clock jitter and to optimize the time taken to recover the clock timing. A further shortcoming is that because the clock frequency component has been removed from the IF signal, the clock signal is lost if the level of the IF signal drops as a result of fluctuations etc. of the propagation path conditions.
The loop filter of a BQDPL clock recovery circuit integrates a control signal that shows the phase lead or lag of the sampling clock signal. In other words, the VCO is controlled after the signal for clock timing recovery has been observed for a long time. Clock jitter can therefore be reduced by increasing the integration time of the loop filter, but this also requires more time to recover the clock timing, so that there is the same problem as encountered with a tank-limiter clock recovery circuit using IF signal operation. Furthermore, more time is required to correct the phase difference between the initial phase of the clock, which is output by the VCO, and the phase of the clock timing which minimizes the bit error rate, as this phase difference becomes larger. A resulting problem is that under normal service conditions, in which the size of the phase difference is not fixed, there will be a spread in the time taken to recover the clock timing. Moreover, because this circuit requires oversampling at two or more times the symbol rate, there are difficulties involved in digital implementation and in coping with increases in the transmission rate of digital data.